China's Chip Breakthrough: How SMIC Defied TSMC's Impossibility

01 The Impossibility Claim

When the United States restricted access to extreme ultraviolet (EUV) lithography machines in 2019, the consensus among semiconductor analysts was that China's domestic chip manufacturing would stall at the 14nm node. EUV lithography, developed by the Dutch company ASML, is the technology that enables patterning at the 7nm and smaller nodes. Without it, the industry orthodoxy held, no foundry could reach the densities that modern processors require. TSMC, Samsung, and Intel all rely on EUV for their advanced nodes. SMIC, China's largest foundry, did not have access to the machines.

That consensus was wrong. In 2023, TechInsights reverse-engineered a Huawei Mate 60 Pro and discovered a 7nm-class Kirin 9000s processor manufactured by SMIC. The chip was fabricated using deep ultraviolet (DUV) multi-patterning, an older technique that requires more exposure passes and yields lower volumes than EUV, but produces functional 7nm-class transistors. The discovery forced a reassessment of how effective export controls could be when applied to a country with China's manufacturing scale and engineering talent.

02 DUV Multi-Patterning: Making Old Tools Do New Work

The technique SMIC used is called self-aligned double patterning (SADP) or quadruple patterning (SAQP), depending on the number of exposure cycles. In DUV lithography, light with a wavelength of 193nm is used to pattern features on a silicon wafer. To print features smaller than the wavelength of the light, engineers split the pattern into multiple exposures, each printing part of the design. The exposures are then combined through a chemical process to create the final pattern.

This approach works but has significant costs. Each additional exposure step increases the number of masks, the time per wafer, and the probability of alignment errors. A chip that requires four patterning passes takes roughly four times as long to fabricate as one that requires a single EUV exposure. The yield, the percentage of chips that function correctly, is also lower because each exposure step introduces potential defects. SMIC's 7nm yield has been estimated at 50-60 percent, compared to TSMC's 80-90 percent on the same node using EUV. This means SMIC must process more wafers to produce the same number of working chips, increasing cost and limiting volume.

03 The Huawei Connection

Huawei's relationship with SMIC is the commercial engine driving China's chip self-sufficiency effort. After US sanctions cut off Huawei's access to TSMC's foundry services in 2020, the company needed a domestic manufacturing partner. SMIC was the only Chinese foundry with the technical capability to attempt advanced-node production. The Kirin 9000s in the Mate 60 Pro was the first commercially significant result of this partnership.

The subsequent Kirin 9010 and 9020 chips, appearing in 2024 and 2025 products, suggest that SMIC is iterating. Each generation has shown modest improvements in transistor density and clock speed, though none match TSMC's 5nm or 3nm performance. The question is whether SMIC can sustain this rate of improvement through DUV alone, or whether the gap will widen as TSMC and Samsung move to 2nm and beyond with next-generation EUV and high-NA EUV systems that China cannot acquire.

04 The Export Control Architecture

The US semiconductor export control regime operates on three pillars: restricting equipment, restricting design software, and restricting access to advanced chips. The equipment pillar targets ASML's EUV machines, which no Chinese company can manufacture. The software pillar targets electronic design automation (EDA) tools from companies like Synopsys, Cadence, and Mentor Graphics, which are essential for designing chips at any advanced node. The chip pillar targets the export of advanced GPUs and AI accelerators, particularly those from NVIDIA, that power large-scale AI training.

The controls have had measurable effects. SMIC cannot buy EUV scanners, and the DUV machines it does have are older immersion models that require multi-patterning for sub-10nm features. Chinese EDA vendors have emerged, but their tools lag behind the Western incumbents in capabilities for the most advanced nodes. And NVIDIA has been prohibited from selling its most powerful data center GPUs in China, though modified versions with reduced interconnect bandwidth have been permitted.

05 The Talent Pipeline

Behind every process node is a team of engineers who understand the physics of lithography, etching, deposition, and metrology. China has invested heavily in semiconductor education, establishing specialized programs at Tsinghua University, Peking University, and the Chinese Academy of Sciences. The country also recruits experienced engineers from TSMC, Samsung, and Western EDA companies, sometimes through attractive compensation packages and sometimes through what Taiwan has characterized as talent poaching.

The Nuvia acquisition by Qualcomm demonstrated that semiconductor talent is globally mobile, and the same principle applies in China's direction. SMIC's engineering team includes veterans from TSMC and other leading foundries. The transfer of tacit knowledge, the kind that is not written in patents or textbooks but lives in the experience of engineers who have debugged yield problems and optimized process recipes, is arguably more valuable than the equipment itself. China's strategy has been to acquire both, legally where possible and through domestic investment where not.

06 The Yield Problem

Manufacturing a working chip at a new process node is not the same as manufacturing it profitably. Yield, the percentage of dies on a wafer that function correctly, determines whether a foundry can sell chips at a competitive price. TSMC's 5nm yields exceeded 80 percent within months of entering production. SMIC's 7nm DUV yields have been estimated at 50-60 percent, which means roughly half the silicon on each wafer is wasted.

Low yields are not a permanent condition. TSMC's early yields at every new node have been lower than mature yields, and the company improves them through a process of statistical analysis and recipe adjustments that can take 12 to 18 months. SMIC has been producing 7nm chips since 2022, and yields have likely improved since then. The question is whether they can reach the 80 percent threshold that would make the node commercially viable for high-volume products, or whether DUV multi-patterning imposes a structural ceiling on yield that EUV does not.

07 Beyond 7nm: The Real Challenge

The 7nm node was a milestone for SMIC, but the next steps are harder. The 5nm and 3nm nodes require EUV in the TSMC and Samsung process flows, and there is no demonstrated path to 5nm using DUV alone. The number of multi-patterning passes required would be so large that the cost per wafer would exceed the cost of an EUV-based process, assuming the yields could even be made acceptable. China's domestic lithography development programs, including those at SMEE (Shanghai Micro Electronics Equipment), are targeting immersion DUV systems but have not demonstrated EUV capability.

This is where the gap may become structural rather than temporal. If SMIC cannot move below 7nm without EUV, and if EUV remains embargoed, then Chinese chip manufacturing will plateau at a node that is two to three generations behind TSMC and Samsung. For many applications, a 7nm chip is sufficient. Smartphone processors, automotive electronics, and most industrial applications do not require the absolute performance of a 3nm or 2nm chip. But for AI training, where the largest GPU dies are built on TSMC's most advanced nodes, the gap matters. China can train AI models on 7nm chips, but it will need more of them, consuming more power and taking more time than a competitor using 3nm hardware.