From Sand to Silicon: How CPUs Are Manufactured

01 The Wafer

A CPU begins as an unusually pure crystal, not as a finished circuit. Silicon is refined, melted, and pulled into a single-crystal ingot whose atomic lattice gives later devices a predictable electrical foundation. A diamond wire saw slices the ingot into wafers, and grinding, polishing, and chemical cleaning make each surface flat enough for patterns measured in nanometers.

The wafer is a shared canvas for many dies. Alignment marks and process controls let a fab repeat hundreds of carefully calibrated steps across its surface. Once fabrication and testing are complete, the wafer is diced into individual chips, so a defect in one region does not necessarily spoil every neighboring die.

02 Photolithography

Photolithography transfers a circuit pattern onto a wafer one layer at a time. The surface receives a light-sensitive photoresist, a patterned reticle controls the exposure, and a developer removes selected regions. The remaining resist becomes a temporary mask for the chemical or physical process that follows.

At the leading edge, extreme ultraviolet lithography uses 13.5 nanometer light to print especially dense layers. The tool is a system rather than a single lamp: a tin-plasma light source, multilayer mirrors, vacuum chambers, precision stages, and computational pattern correction all have to work together. Smaller printed features are valuable, but overlay accuracy and defect control are equally important.

03 Etching and Deposition

After exposure, etching removes material from the unprotected regions. Plasma chemistry can make the cut highly directional, allowing narrow trenches and contact holes to be formed without eroding the pattern sideways. Because each layer is thin and the geometry is crowded, the process must control selectivity, profile shape, residue, and damage to the underlying film.

Deposition does the opposite: it adds films to the wafer. Chemical vapor deposition, physical vapor deposition, and atomic layer deposition place conductors, insulators, barriers, and sacrificial materials where the process flow needs them. Repeated deposition and etch cycles build the stack of a modern chip, while planarization polishes the surface back to a controlled level before the next pattern is printed.

04 Doping

Pure silicon is not enough to make a useful switch. Doping introduces carefully selected impurity atoms that change the concentration and type of mobile charge carriers. Boron can create p-type regions; phosphorus or arsenic can create n-type regions. Ion implantation accelerates those atoms into the crystal, and a thermal anneal repairs lattice damage while activating the dopants.

The dose, energy, temperature, and geometry all matter. A source and drain need different electrical properties from a channel, and abrupt junctions help keep current under control. Modern process integration often combines implantation with epitaxial growth and highly engineered contact materials, because a transistor's performance depends on the entire path from gate to interconnect.

05 The Transistor at Billions Scale

A transistor is a controllable switch: a gate voltage changes the conductivity of a channel between source and drain. Planar gates eventually struggled with leakage and electrostatic control as dimensions shrank. FinFETs improved control by wrapping the gate around a raised silicon fin on multiple sides, increasing effective gate contact without requiring a proportionally wider footprint.

Gate-all-around, or GAA, devices take that idea further. The channel becomes a horizontal sheet or nanowire surrounded by the gate, so the gate has stronger control on every side. This is why a process node is not just a ruler measurement. It names a generation of design rules, transistor architecture, materials, interconnects, and yield targets that together determine performance per watt and usable density.

06 The Fab

A leading-edge fab is a controlled environment for chemistry, mechanics, optics, and data. Air is filtered repeatedly, temperature and vibration are tightly managed, and wafers move through automated tracks and metrology tools. The room above the floor is only part of the facility: utilities for ultrapure water, gases, power, waste treatment, and tool maintenance are fundamental to production.

The capital bill is correspondingly immense. A fab must buy specialized equipment, qualify recipes, ramp yield, and keep enough capacity to make the economics work. EUV scanners are among the most complex machines ever built, but lithography is only one link in a chain that includes deposition, etch, inspection, packaging, and design software. A few percentage points of yield can separate a profitable process from an expensive experiment.

07 The AI Chip Connection

The AI boom is often described in terms of models, but models run on physical systems. CPUs coordinate data movement, storage, operating systems, and preprocessing; GPUs and other accelerators perform much of the parallel tensor math. The performance of the whole system depends on memory bandwidth, packaging, networking, power delivery, and the ability to manufacture enough reliable devices.

That makes semiconductor fabrication a strategic bottleneck. Smaller and more efficient transistors can improve compute per watt, while advanced packaging can place logic beside high-bandwidth memory and shorten the distance data must travel. Demand from AI therefore reaches backward through foundries, equipment suppliers, materials companies, and energy infrastructure. The chip is not a passive container for intelligence; it is part of the economics and limits of the intelligence being deployed.