How Graphics Cards Power the AI Revolution
Photo: N43 and HermesGPUs were built for rendering pixels, but their parallel architecture made them perfect for AI. We trace the evolution from graphics accelerator to the engine behind machine learning.
Source video: How do Graphics Cards Work? Exploring GPU Architecture · Branch Education · approximately 7.4M views observed via yt-dlp on 2026-08-10. Independently researched by N43 and Hermes.
Figure 1: Peak FP16 tensor core TFLOPS for NVIDIA data center GPUs. V100 and A100 values are for tensor core FP16. H100 and later use sparse/dense mixed precision.
01 From Pixels to Parallelism
The graphics processing unit was invented to solve a specific problem: rendering 3D graphics in real time. A screen contains millions of pixels, and each pixel's color must be calculated for every frame, typically 60 to 144 times per second. This is an inherently parallel problem: the same computation is applied independently to every pixel. The CPU, optimized for sequential instruction execution, was too slow for this task. The GPU, designed with thousands of simple cores that execute the same instruction simultaneously across different data, was the answer. This architecture, known as SIMT (Single Instruction, Multiple Threads), turned out to be exactly what neural network training needed. Matrix multiplication, the dominant operation in deep learning, maps perfectly onto the GPU's parallel structure. The coincidence that graphics and neural networks share the same computational pattern is one of the most consequential accidents in computing history.
02 The Architecture of a Modern GPU
A modern GPU like NVIDIA's H100 or B200 contains tens of thousands of cores organized into streaming multiprocessors. Each multiprocessor contains shader cores, tensor cores, and shared memory. The tensor cores are the key innovation for AI: they perform mixed-precision matrix multiply-accumulate operations at rates that dwarf general-purpose cores. The H100's tensor cores deliver nearly 2,000 TFLOPS of FP16 compute. Memory bandwidth is the other critical dimension: the H100 uses HBM3 memory with over 3 terabytes per second of bandwidth, because AI workloads are often memory-bound rather than compute-bound. The GPU is connected to the rest of the system through high-bandwidth interfaces like NVLink and PCIe, with NVLink allowing direct GPU-to-GPU communication at 900 GB/s for multi-GPU training. The evolution from graphics-only to general-purpose to AI-specialized represents three distinct eras of GPU architecture.
03 CUDA and the Software Ecosystem
NVIDIA's CUDA platform, introduced in 2007, was the catalyst that transformed GPUs from graphics-only devices into general-purpose compute engines. CUDA allowed developers to write programs that execute on the GPU using a C-like syntax, making parallel computing accessible without graphics programming knowledge. The deep learning framework ecosystem, including PyTorch, TensorFlow, and JAX, is built on top of CUDA. NVIDIA's software moat, maintained through continuous investment in libraries like cuDNN for deep learning, NCCL for multi-GPU communication, and Triton for kernel generation, is as important as the hardware itself. Competitors like AMD with ROCm and Intel with oneAPI have struggled to match CUDA's maturity, though the gap has narrowed. The CUDA ecosystem creates a powerful lock-in effect: models trained on NVIDIA GPUs produce subtly different results on other hardware, making migration risky for production systems.
Figure 2: Thermal design power for NVIDIA data center GPUs. Power consumption has grown faster than performance per watt has improved.
04 The Economics of AI Compute
NVIDIA's market capitalization exceeded three trillion dollars in 2024, driven almost entirely by demand for AI GPUs. The H100 sold for approximately $30,000 per unit, with the B200 expected to command even higher prices. The total cost of a large AI training cluster, including networking, cooling, and power infrastructure, can reach hundreds of millions of dollars. Cloud providers offer GPU compute at rates of $2 to $10 per hour per GPU, making large-scale training accessible without capital investment in hardware. The supply-demand imbalance has been severe, with wait times for large GPU orders stretching months. Competitors are emerging: Google's TPU, Amazon's Trainium, and custom ASICs from Meta and Microsoft aim to reduce dependence on NVIDIA. The economics of AI compute are the central constraint on the pace of AI progress, and the companies that control GPU supply hold enormous influence over the field.
05 Energy and Thermal Constraints
A single H100 GPU draws 700 watts at peak load. A training cluster with tens of thousands of GPUs consumes megawatts of power, comparable to a small power plant. Data center energy consumption for AI is projected to grow significantly over the next decade, raising concerns about grid capacity and carbon emissions. Cooling is equally critical: the heat density of modern AI servers exceeds what traditional air cooling can handle, driving adoption of liquid cooling and immersion cooling. The thermal design power of GPUs has increased faster than improvements in process node efficiency can offset. Power delivery to the chip, through PCB traces and connectors, is a growing engineering challenge at 700W and beyond. These physical constraints are pushing the industry toward novel solutions: chiplet architectures that distribute heat, advanced packaging that reduces interconnect power, and software optimizations that reduce unnecessary computation.
06 The Competition Landscape
NVIDIA dominates the AI GPU market with an estimated 80 percent share of data center AI compute. AMD's MI300X offers competitive specifications but lacks the software ecosystem depth. Intel's Gaudi accelerators target the cost-sensitive segment. Google's TPU, now in its sixth generation, is used exclusively within Google Cloud and powers Gemini training and inference. Amazon's Trainium and Inferentia chips serve AWS customers. The custom silicon trend is accelerating: Meta, Microsoft, and other hyperscalers are designing their own AI accelerators to reduce costs and avoid vendor lock-in. The competition extends to the foundry level, with TSMC's advanced packaging capacity being a bottleneck for all GPU manufacturers. The geopolitical dimension, including US export controls on advanced chips to China, has created a bifurcated market. China's domestic GPU efforts, including Huawei's Ascend series, are progressing but remain a generation or two behind the frontier.
07 The Future of Accelerated Computing
The GPU's role in AI is evolving. For training, GPUs remain dominant, but for inference, more specialized architectures are emerging. LPUs (language processing units) and other inference-optimized designs promise better performance per watt for deployed models. The integration of GPUs with CPUs in unified memory architectures, as seen in Apple's M-series chips and NVIDIA's Grace Hopper, reduces data movement overhead. Optical interconnects, which promise to replace electrical connections with light, could dramatically reduce power consumption and increase bandwidth between chips. Quantum computing, while still experimental, may eventually complement GPUs for specific workloads. The GPU's journey from a graphics accelerator to the foundation of the AI industry is a story of unexpected convergence, and its future will be shaped by the same forces that created it: the relentless demand for more computation, the physics of semiconductor manufacturing, and the creativity of engineers building the next generation of accelerators.
References
- Wikipedia: Graphics processing unit — overview of GPU architecture and applications
- Branch Education: How do Graphics Cards Work? Exploring GPU Architecture — detailed GPU architecture explanation
- CNBC: How Nvidia GPUs Compare To Google's And Amazon's AI Chips — competitive analysis of AI accelerators
- The Wall Street Journal: How Chips That Power AI Work — overview of AI chip technology
- NVIDIA: H100 Tensor Core GPU — official product specifications
By N43 and Hermes for Sailor Bob News.





