How Microchips Are Fabricated At Nanoscale

Source: The World's Most Important Machine by Veritasium (34M views)

01 From Sand To Silicon: The Wafer Begins

Every microchip begins as quartz sand, melted and purified into a single crystal silicon ingot known as a boule. The boule is grown using the Czochralski process, where a seed crystal is dipped into molten silicon and slowly pulled upward while rotating, forming a perfect single-crystal cylinder up to 300mm in diameter and over two meters long. This cylinder is then sliced into wafers thinner than a millimeter, polished to mirror flatness. A single 300mm wafer — the industry standard since the year 2000 — can yield hundreds of individual chip dies, each containing billions of transistors. The purity requirements are staggering: semiconductor-grade silicon must be 99.999999999% pure — meaning fewer than one impurity atom per billion silicon atoms. Even a single stray particle of dust landing on a wafer during processing can destroy an entire batch of chips, which is why fabrication plants maintain cleanrooms thousands of times cleaner than a hospital operating theater.

02 Photolithography: Printing Circuits With Light

The heart of chip fabrication is photolithography — the process of using light to print microscopic circuit patterns onto the silicon wafer. A photosensitive chemical called photoresist is applied to the wafer surface, then ultraviolet light is projected through a photomask (a stencil containing the circuit design) using a lens system that shrinks the pattern to nanometer scale. The light chemically alters the photoresist, and the exposed (or unexposed) areas are washed away, leaving the circuit pattern etched into the surface. This process is repeated dozens of times — a modern 3nm chip may go through 60 to 80 lithography steps, each layering a different part of the transistor structure and interconnect wiring. The critical challenge is wavelength: to pattern features smaller than the wavelength of light itself, manufacturers have pushed through successive generations of light sources, from 248nm krypton-fluoride lasers to 193nm argon-fluoride lasers, and now to extreme ultraviolet (EUV) at just 13.5nm — a wavelength generated by firing lasers at molten tin droplets 50,000 times per second.

03 EUV Lithography: The Most Complex Machine Ever Built

The EUV lithography machines built by ASML — the Dutch company featured in Veritasium's documentary — are widely considered the most complex machines ever constructed. Each machine costs over $200 million and contains roughly 100,000 individual parts. To generate 13.5nm EUV light, the system fires a high-power CO2 laser at microscopic droplets of molten tin, falling through a vacuum chamber at 50,000 droplets per second. Each droplet is hit twice: first to flatten it, then to vaporize it into plasma that emits EUV light. This light is collected by the most perfect mirrors ever made — multilayer Bragg reflectors made of alternating molybdenum and silicon layers, each just nanometers thick. EUV light is absorbed by virtually everything, including air, so the entire optical path must operate in a vacuum. Only one company on Earth — ASML — can build these machines, and they produce fewer than 100 per year. Every advanced chip on the planet, from Apple's A-series to AMD's Ryzen, is manufactured using ASML EUV systems.

04 Etching, Deposition, And Ion Implantation

Once the photoresist pattern is in place, the wafer undergoes a series of chemical and physical processes. Etching removes exposed silicon or oxide to create the physical structures of transistors. Dry etching using plasma (reactive ion etching) provides the precise, anisotropic removal needed for nanometer-scale features. Deposition adds thin films of material — silicon dioxide, silicon nitride, or metals like copper and tungsten — using chemical vapor deposition (CVD) or physical vapor deposition (PVD). Ion implantation shoots dopant atoms (boron, phosphorus, or arsenic) into the silicon at high velocity to modify its electrical properties, creating the source and drain regions of each transistor. A single modern chip requires 50 to 80 of these deposition and etching cycles, with the wafer traveling between hundreds of different machines in the fab, transported inside sealed FOUPs (front-opening unified pods) that maintain a nitrogen atmosphere to prevent contamination. The entire fabrication process for an advanced node takes 11 to 15 weeks.

05 The FinFET Revolution And 3D Transistors

As transistors shrank below 22nm, traditional planar (flat) transistors began suffering from short-channel effects — current leaked even when the switch was off. The solution was the FinFET, a three-dimensional transistor architecture first demonstrated by Intel in 2011 at the 22nm node. In a FinFET, the transistor channel rises vertically from the wafer like a fin, with the gate electrode wrapping around three sides of the fin, providing far better control of current flow. At the 3nm node and beyond, manufacturers have moved to gate-all-around (GAA) transistors, where the gate surrounds the channel on all four sides. Samsung's 3nm GAA process and TSMC's planned 2nm GAA node represent the bleeding edge of transistor design. Each generation roughly doubles transistor density and improves power efficiency by 15 to 30%, sustaining the cadence of Moore's Law — the empirical observation, first articulated by Gordon Moore in 1965, that the number of transistors per integrated circuit doubles approximately every two years.

06 Packaging, Testing, And Yield

After fabrication, the completed wafer is tested and individual dies are separated by diamond sawing or laser dicing. Each die is then packaged — enclosed in a protective ceramic or plastic housing with electrical connections to the outside world. Modern advanced packaging goes far beyond simple encapsulation: chiplet architectures split a large monolithic die into smaller pieces and reconnect them on a silicon interposer, improving yield (since smaller dies are less likely to contain a defect) and allowing different process nodes to be mixed on the same package. Yield — the percentage of functional dies on a wafer — is the single most important economic metric in semiconductor manufacturing. A mature process may achieve 90%+ yield, but a new node typically starts below 50% and takes months or years to mature. At $20,000 to $30,000 per 300mm EUV wafer, even small yield improvements translate to enormous cost savings. The most advanced fabs — operated by TSMC, Samsung, and Intel — each cost $15 to $20 billion to build, making semiconductor fabrication one of the most capital-intensive industries on Earth.

07 The Geopolitics Of Chip Manufacturing

Veritasium's documentary highlights a startling concentration: over 90% of the world's most advanced chips are manufactured in a single country — Taiwan. TSMC alone produces roughly 60% of the world's semiconductors and over 90% of the most advanced ones. This geographic concentration has made semiconductor manufacturing a focal point of geopolitical tension, particularly between the United States and China. The CHIPS and Science Act, signed into law in 2022, allocated $52 billion in subsidies to bring advanced chip manufacturing back to the US, spurring TSMC, Samsung, and Intel to build new fabs in Arizona, Texas, and Ohio. Meanwhile, China has invested heavily in domestic lithography capability, though it remains generations behind ASML in EUV technology. The supply chain spans the globe: design tools from the US (Synopsys, Cadence), lithography from the Netherlands (ASML), chemicals from Japan (JSR, Shin-Etsu), and assembly and packaging from Southeast Asia. A disruption to any single link — as demonstrated during the 2020-2023 chip shortage — can cascade across the entire global economy, affecting everything from automobiles to smartphones to military systems.