How Microchips Are Made: From Sand to the Silicon Brains of Modern AI

01 From Sand to Stacks: Why Chips Begin as Rocks

A microchip starts its life as some of the most ordinary material on Earth: silicon dioxide, the main component of sand and quartz. What makes silicon special is not rarity but physics. It is a semiconductor, meaning its conductivity sits between that of a metal and an insulator, and it can be switched on and off with exquisite precision by applying tiny voltages. That switchability is the root of all digital computation, and it is why roughly thirty percent of the crust of the planet, by element, ultimately feeds the computing industry.

The jump from beach sand to chip-grade silicon is a story of purification to absurd extremes. Quartz is refined first into metallurgical-grade silicon at around 98 percent purity, which is still not nearly pure enough. Through chemical processes such as the Siemens method, raw silicon is converted into volatile compounds and then re-deposited as polysilicon rods purified to 99.9999999 percent, a purity level industry people call "nine nines." At that concentration, you would find fewer stray atoms in a silicon crystal than there are people in a small town inside a chunk the size of a car.

Why does purity matter so much? Because a modern transistor is a landscape measured in nanometers. Any stray atom of iron or copper wandering into the crystal lattice becomes an electrical landmine, degrading or killing the devices built on top of it. The entire manufacturing pipeline downstream, worth tens of billions of dollars in fab equipment, exists on the assumption that the incoming silicon is nearly atomically flawless. That assumption is what allows engineers to print billions of working devices on a wafer and still expect a profitable yield.

02 Crystal Growth and the Perfect Wafer

Polysilicon is not yet usable. Chips need monocrystalline silicon, in which every atom across the entire ingot sits in a single, continuous lattice. To get there, manufacturers use the Czochralski process: a small seed crystal of perfect silicon is dipped into a crucible of molten polysilicon and then slowly drawn upward while rotating. As it is pulled, silicon atoms from the melt lock onto the seed and replicate its lattice, forming a cylindrical ingot that can grow over a meter long and weigh hundreds of kilograms. The ingot is then ground to an exact diameter and sliced with diamond saws or wire into thin discs called wafers.

Today the industry standard is the 300-millimeter wafer, roughly the size of a dinner plate and sliced to a thickness of well under a millimeter. Each wafer is polished to a mirror finish, because the photolithography that follows is essentially an optical printing process, and optical printing is only as good as its canvas. Any scratch, warp, or particle on the wafer surface will print its defect into every layer stacked above it, so wafers are finished to a flatness measured in fractions of a nanometer across their entire surface.

The economics of the wafer explain much of the industry's structure. A single 300-millimeter wafer can yield hundreds or thousands of identical dies, so the per-chip cost of the silicon itself is small. The enormous fixed costs of the fab, the machines, and the process engineering dominate instead. That is why manufacturing gravitated toward a handful of giant, hyper-specialized foundries, and why wafer supply, not raw sand, is the real chokepoint the industry watches.

03 Photolithography: Printing Circuits With Light

Photolithography is the heart of chipmaking and the reason the industry talks about "printing" transistors. The wafer is coated with a light-sensitive chemical called photoresist. Light is projected through a patterned mask, called a photomask or reticle, which casts a shrunken image of the circuit pattern onto the resist. Wherever light strikes, the resist changes chemically, so a subsequent development step dissolves the exposed regions and leaves a stencil of the pattern on the wafer. Light plus chemistry turns an abstract circuit diagram into a physical template.

The resolution problem is everything. For decades, chipmakers shrank features by using shorter and shorter wavelengths of light, from visible light in the 1970s down to deep ultraviolet at 248 nanometers and then 193 nanometers. When the wavelength stopped shrinking, engineers squeezed out more resolution with cleverness instead: immersion lithography places a thin layer of purified water between the lens and the wafer to increase the effective numerical aperture, and multi-patterning splits one dense pattern into several sequentially printed, interleaved exposures. The cost of that cleverness is cycle time and complexity, and every extra exposure step is another chance for defects.

The scale is hard to grasp without a chart. The first commercial microprocessor, the Intel 4004 of 1971, carried 2,300 transistors. A flagship AI accelerator in the mid-2020s carries on the order of two hundred billion, spread across multiple stacked dies. That eight-decade climb, a doubling roughly every two years, is Moore's Law in action, and it was achieved almost entirely by repeatedly improving lithographic resolution and the process steps wrapped around it.

04 Etching, Doping, and the Art of Layering

Lithography alone builds nothing; it only draws the stencil. The next two steps do the actual sculpting. In etching, the wafer is bathed in plasma or reactive chemicals that remove the exposed material not protected by the remaining photoresist, carving the pattern into the underlying film. In doping, ions of elements such as boron or phosphorus are fired into the silicon at precisely controlled depths and doses, surgically modifying its electrical character to form the sources, drains, and channels of transistors. Modern ion implanters accelerate dopant atoms to hundreds of kilometers per second and place them with atomic-layer accuracy.

One lithography-etch-deposit cycle creates one layer of features, but a modern chip is not a flat drawing; it is a vertical city. Transistors are formed first at the wafer surface, then interconnect layers, tiny wiring stacks of copper damascene embedded in insulating dielectric, are built above them, floor by floor, to wire the billions of devices together. Flagship logic chips stack a dozen or more metal layers, each requiring its own masks, lithography passes, etch steps, chemical mechanical polishing to re-flatten the surface, and defect inspection. All told, a leading-edge wafer passes through well over a thousand individual process steps over roughly three months inside the fab.

The compounding mathematics of yield is what keeps fab engineers awake. If any single step has even a one percent chance of ruining a die, and there are over a thousand steps, virtually nothing would survive. Every process in the fab must be reliable at success rates far beyond what most industries consider high quality, which is why fabs run around the clock in bunny suits under ISO cleanliness thousands of times stricter than a hospital operating theater. A single human hair, or even a particle of skin, is enormous compared to a transistor, so people themselves are the biggest contamination threat inside the cleanroom.

05 The EUV Era and the Leading-Edge Race

By the early 2010s, 193-nanometer immersion lithography with multi-patterning was running out of road, and the industry needed a fundamentally new light source. The answer took decades to commercialize: extreme ultraviolet lithography, or EUV, which uses 13.5-nanometer light. Producing that light is almost absurdly violent. A machine built by ASML fires fifty thousand droplets of molten tin per second, each hit twice by high-power carbon dioxide lasers, turning the tin into plasma that radiates EUV photons. The light is then reflected and focused through a series of the smoothest mirrors ever manufactured, because EUV is absorbed by virtually everything, including air, so the entire optical path runs in vacuum. Each machine is the size of a bus and sells for well over one hundred million dollars, with next-generation high-NA versions approaching four hundred million.

EUV entered high-volume manufacturing at the 7-nanometer node around 2018 and now underpins the 5, 4, 3, and 2-nanometer generations. One subtlety deserves emphasis: modern node names are marketing labels, not physical measurements. A "3-nanometer" chip does not have 3-nanometer transistors; the most critical dimensions are several times larger. The names persist because they mark generations of density improvements, roughly doubling logic density every couple of years, and because customers, investors, and journalists need a shorthand for progress.

The node race has also concentrated the industry geographically to a degree almost unique in manufacturing. Only three companies operate leading-edge logic fabs at scale, TSMC, Samsung, and Intel, and TSMC fabricates the overwhelming majority of the world's most advanced chips, including the majority of AI accelerators and flagship smartphone processors. A single company in the Netherlands makes the EUV machines, a handful of Japanese firms make the photoresists, and a few suppliers make the specialty gases and ultra-pure water. The pipeline from sand to AI is global by necessity, which makes it fragile by design, a lesson the world learned the hard way between 2020 and 2023.

06 Packaging, Testing, and the Cost of a Single Speck

After months in the fab, finished wafers are probed with automated test equipment before they are even cut apart. Every die is tested electrically, and a map of passing and failing chips is built for each wafer. Defects, a stray particle, a slightly misaligned exposure, a bit of contamination in an etch bath, cluster randomly, so yield is a statistical game. Fabs sell chips at enormous margins precisely because a large share of what they produce can die silently at this stage, and mature processes with yields in the high ninety-percent range subsidize the bleeding-edge nodes where yields are far lower.

Dies that pass are singulated, sawn apart from the wafer, and then packaged: mounted on a substrate, connected to the outside world through fine bond wires or copper pillars, and sealed against moisture, heat, and shock. Packaging used to be the boring end of the industry, but it has become a frontier of its own. Because lithography and transistor scaling have slowed, designers now win performance by stacking and side-by-side techniques called advanced packaging: chiplets partitioned into multiple dies on an interposer, cache stacked directly on top of logic, and memory bonded near the compute die. The AI accelerators of the mid-2020s are not one chip but small clusters of silicon stitched together in the package.

That shift has consequences. Advanced packaging capacity, not just wafer capacity, became a genuine bottleneck for AI hardware, with interposer and bonding tooling suddenly on the critical path for every accelerator shipment. The final product a data center receives is thus the endpoint of an unbroken chain: quartz, ingot, wafer, over a thousand process steps, EUV photons from vaporized tin, and packaging precision measured in microns. Break any link and nothing downstream exists.

07 What the Chip Shortage Taught the World

Between 2020 and 2023 the world ran an unplanned experiment on what happens when this pipeline hiccups. Pandemic disruptions, surging demand for consumer electronics, a fire at a key Japanese fab, drought in Taiwan, and shipping snarls cascaded into a global shortage. Carmakers were hit hardest because they had canceled chip orders early in the pandemic, expecting slow sales, and then discovered that a modern vehicle contains a thousand or more chips, from engine management to seat controllers. Industry estimates placed automaker revenue losses in the hundreds of billions of dollars, all for want of components costing a few dollars each.

The shortage revealed how opaque and rigid the supply chain is. Chips must be ordered months in advance, and a fab cannot retool to make a different part on short notice; a line qualified for a power management chip cannot simply start printing microcontrollers. Governments responded by treating semiconductors as strategic infrastructure: the United States, the European Union, Japan, and India all launched multibillion-dollar subsidy programs to attract fab construction, and the United States CHIPS and Science Act reshaped corporate investment plans. Building fabs, however, takes years, so the immediate effect of the shortage was a boom in capacity announcements that will mature on political timescales, not consumer ones.

The market data tells the story of the whiplash. Global semiconductor sales jumped sharply in 2021 and 2022 as everyone hoarded and over-ordered, dipped in 2023 when that inventory unwound, and then surged to a new record in 2024 as AI hardware demand took over from consumer electronics. The shortage is gone, but the lesson stuck: a supply chain optimized for efficiency turned out to have almost no slack, and no amount of software can fix a missing chip.

08 Why Every AI Ambition Runs Through a Fab

The AI boom is often narrated in terms of models, parameters, and data centers, but beneath every training run is a manufacturing achievement. The GPUs, TPUs, and NPUs that train and serve frontier models are the densest logic chips ever fabricated, and they are only possible because every stage of the pipeline described above works at once: nine-nines silicon, EUV lithography, hundreds of wiring layers, and chiplet packaging that stitches multiple reticle-sized dies into one logical accelerator. When a company announces a faster model, it is quietly also announcing that someone managed to print, wire, and yield an enormous quantity of near-atomic-scale hardware.

This dependency shapes strategy at the highest levels. Export controls on advanced chips are, mechanically, controls on who may receive the output of specific fab lines. National AI ambitions are increasingly expressed as fab subsidies, packaging capacity, and lithography supply, because a country without access to leading-edge silicon has a ceiling on its AI capabilities no matter how strong its software sector is. The smartphone in your pocket and the model answering your questions sit at the end of the same fragile, hyper-global supply chain, one that begins with sand and passes through the most expensive, precise, and clean manufacturing environment humans have ever built.

The TED-Ed explainer that prompted this analysis compresses the pipeline into a five-minute animation, and it is a rare case where a subject genuinely deserves the compression. From Czochralski ingots to tin-vaporizing EUV sources, microchip manufacturing is the physical substrate of the information age, and understanding it, silicon, light, plasma, and copper stacked by the trillion, is a prerequisite for understanding where computing, and AI, can physically go next.