How Microchips Are Made: The Semiconductor Manufacturing Process

01 From Quartz to Crystal: Growing the Silicon Ingot

Every microchip begins as quartz sand, specifically the high-purity silica that can be refined into metallurgical-grade silicon through carbothermic reduction in an electric arc furnace at temperatures above 1900 degrees Celsius. That raw silicon, roughly 98 percent pure, is then converted to trichlorosilane gas, distilled to remove impurities, and decomposed back into elemental silicon through a process called the Siemens reaction. The result is polysilicon with impurity levels below one part per billion.

From this ultrapure polysilicon, a single crystal is grown using the Czochralski process. A seed crystal is dipped into a crucible of molten silicon and slowly withdrawn while rotating, pulling a monocrystalline ingot — or boule — upward. The ingot can reach 300 millimeters in diameter and two meters in length, with its crystal lattice so regular that the positions of individual atoms are predictable across the entire volume. After growth, the boule is ground to a precise diameter, sliced into wafers with a diamond-coated wire saw, and polished to a mirror finish with surface roughness measured in angstroms.

02 Photolithography: Printing Circuits With Light

The defining operation in semiconductor fabrication is photolithography, a photographic process that transfers a circuit pattern onto the wafer. The wafer is first coated with a light-sensitive polymer called photoresist, then exposed through a photomask using ultraviolet light projected by a stepper or scanner. Where the light strikes, the resist undergoes a chemical change that allows a developer solution to wash away the exposed regions, leaving a stencil of the circuit features etched into the resist layer.

The wavelength of the light sets the fundamental limit on how small a feature can be printed. For decades, manufacturers used deep ultraviolet light at 193 nanometers produced by argon-fluoride excimer lasers. The transition to extreme ultraviolet at 13.5 nanometers, commercialized by ASML starting in the late 2010s, required replacing refractive optics with reflective mirrors and operating the entire optical path in vacuum because air absorbs 13.5-nanometer photons. EUV systems now cost upwards of $200 million per unit and consume an order of magnitude more power than their predecessors.

03 Deposition, Etching, and Doping

Once the resist pattern is in place, the wafer undergoes a sequence of thin-film deposition and etching steps. Chemical vapor deposition grows layers of material — silicon dioxide, silicon nitride, polycrystalline silicon, or metals such as copper and tungsten — by reacting precursor gases on the wafer surface. Physical vapor deposition, including sputtering and evaporation, deposits metal films without a chemical reaction. Each layer may be only a few nanometers thick, and a finished chip can contain more than 80 distinct layers stacked vertically.

Etching removes material from regions not protected by the resist stencil. Wet etching uses liquid chemicals that dissolve the exposed film isotropically, undercutting the mask in some directions. Dry etching with reactive ion etching provides directional, anisotropic removal that preserves vertical sidewalls and is the dominant technique at modern process nodes. Between etching steps, ion implantation shoots dopant atoms — boron, phosphorus, or arsenic — into the silicon at precisely controlled energies, altering the electrical conductivity of selected regions to form the source and drain terminals of each transistor.

04 The Transistor Shrink: From Planar to FinFET to GAA

For most of the integrated circuit era, the workhorse transistor was the planar MOSFET, a flat device with a gate electrode sitting above a channel that ran along the wafer surface. Shrinking the planar transistor below 28 nanometers ran into short-channel effects: as the gate length decreased, the gate lost control over the channel, and the transistor could not be turned off cleanly. Leakage current soared, and power consumption became unmanageable.

The industry responded with the FinFET, a three-dimensional transistor architecture in which the channel rises as a fin above the wafer and the gate wraps around three sides of it. First commercialized by Intel at the 22-nanometer node in 2011, the FinFET restored gate control and dominated manufacturing for a decade. At the 3-nanometer node and below, even the FinFET runs out of room. The successor is the gate-all-around transistor, in which the channel is a nanosheet stacked horizontally and the gate wraps fully around all four sides. Samsung introduced GAA at 3 nanometers in 2022, and TSMC is following at the 2-nanometer node.

05 Yield, Defects, and the Economics of the Fab

A fabrication plant, or fab, is among the most expensive industrial facilities ever built. A leading-edge logic fab now costs between $15 billion and $20 billion to construct, and each wafer processed through it may traverse 500 to 1000 individual steps over two to three months. At the end of that pipeline, the wafer is diced into individual chips, and the fraction that function correctly is called the yield. At a mature node, yields above 90 percent are routine. When a new node first enters production, yields can be below 50 percent and climb over months as the process is refined.

Defects are the enemy of yield. A single particle of dust landing on a wafer during a critical step can short-circuit a chip, and because modern chips pack billions of transistors into a square centimeter, the tolerance for contamination approaches zero. Fabs maintain cleanrooms at ISO Class 1 or better, meaning fewer than 10 particles per cubic meter of air, and every chemical and gas entering the process is filtered to parts-per-trillion purity. The economics are brutal: a single processed 300-millimeter wafer at the 3-nanometer node can cost $20,000 or more, and a bad die on that wafer represents unrecoverable loss.

06 Packaging: From Die to Device

The finished wafer is tested, diced into individual die, and the known-good die are packaged for integration into electronic systems. Traditional packaging bonds the die to a lead frame and encloses it in a ceramic or plastic body with pins or solder balls for mounting on a printed circuit board. This approach is inexpensive but routes all electrical signals through a relatively small number of interconnects at the package boundary.

Advanced packaging has become a critical frontier as Moore's Law at the single-die level slows. 2.5D integration places multiple die side by side on a silicon interposer with fine-pitch interconnects, allowing a processor and high-bandwidth memory to communicate at far higher bandwidth than traditional packaging allows. 3D stacking bonds die vertically with through-silicon vias connecting them through the substrate of the silicon itself. AMD, Intel, TSMC, and Samsung are all investing heavily in chiplet architectures, where a large chip is decomposed into smaller die fabricated at different nodes and reassembled in a single package. The boundary between chip design and packaging is dissolving.

07 The Geographic Concentration Problem

Modern semiconductor manufacturing is geographically concentrated to a degree that few industries can match. As of 2026, Taiwan produces roughly 90 percent of the world's most advanced logic chips, almost all through TSMC. The Netherlands is home to ASML, the sole producer of EUV lithography systems. Japan dominates photoresist supply. South Korea leads in memory fabrication. This concentration creates systemic risk: a single geopolitical disruption could halt the flow of advanced chips to the global economy.

The response is a wave of government-backed investment in geographic diversification. The U.S. CHIPS and Science Act, the European Chips Act, and parallel programs in Japan and India are directing hundreds of billions of dollars toward new fabrication capacity. TSMC is building fabs in Arizona and Japan; Samsung is expanding in Texas; Intel is investing in Ohio and Germany. But building a fab is the easier half of the problem. Cultivating the dense ecosystem of equipment suppliers, materials companies, and trained engineers that makes a fab operable is harder, and the talent pipeline takes a generation to build.