Huawei's Ascend 910C and the Arithmetic of China's AI Compute Gap

01 What the 910C Physically Is

Physically, the Ascend 910C is not one chip but two: a dual-die package that combines two Ascend 910B dies on a single substrate, joined by an on-package interconnect and presented to the host system as one accelerator. The dies are fabricated on SMIC's 7nm-class N+2 process, the densest node the Chinese fab ecosystem currently produces at volume under export controls. The design is a pragmatic answer to a physical ceiling: when a single die cannot grow, put two of them in one package.

Huawei does not publish full specifications for the part, which is unusual for a product of this scale and consequential for anyone evaluating it. Every performance figure in circulation is analyst-reported, field-measured, or inferred from teardowns. This article treats those numbers as estimates rather than specifications, and the distinction matters: a vendor datasheet can be audited, an approximation cannot.

02 The Spec Sheet Against the H100

Even with estimated inputs, the comparison against published NVIDIA specifications is legible. Analyst-reported figures put the 910C at roughly 3.2 TB/s of memory bandwidth and in the 780 to 800 TFLOPS class for BF16 compute. The H100 SXM, by contrast, is specified at 3.35 TB/s and approximately 990 TFLOPS of dense BF16, and the newer B200 pushes bandwidth to roughly 8 TB/s. On paper the 910C trails the H100 by high single-digit percentages on bandwidth and roughly a fifth on dense compute, and trails the current generation by far more.

The honest reading is that the 910C competes with a chip introduced in 2022, not with the frontier part of 2026, and the deficit closes one architecture per cycle rather than per year. That framing is neither triumphal nor dismissive; it is what the numbers support. Everything that follows - yields, software, interconnect - determines whether the paper gap widens or narrows in practice.

03 The Yield Problem

Yields are the quiet constraint behind every 910C shipment. SMIC reaches its 7nm-class node through DUV multi-patterning, which multiplies lithography passes, and every additional pass multiplies the defect opportunities that decide whether a die functions. Yields on such processes run materially below the EUV-based equivalents available to unrestricted fabs, and the gap is paid per wafer, every week, at scale.

The dual-die design compounds the risk, because a package only works when both dies work, so the fraction of usable packages falls faster than the fraction of good dies. Constrained HBM supply adds a third tax: high-bandwidth memory remains one of the hardest components to source domestically, and a modern accelerator is starved without it. Volume, not brilliance, is the binding constraint on the Ascend fleet.

04 The Software Moat: CANN Versus CUDA

Hardware is the smaller half of the gap. The larger half is software: Huawei's CANN toolkit and MindSpore framework against more than a decade of CUDA ecosystem lock-in. Nearly every production model, kernel library, and optimization recipe in the industry assumes NVIDIA's programming model, and CANN must reimplement that surface while matching expectations formed on foreign hardware. Frameworks now expose backends beyond CUDA, and major Chinese labs have ported flagship models to Ascend, which narrows the gap at the top of the stack.

The moat survives at the bottom. Kernel-level performance work is where training efficiency lives, and that layer accumulates through person-decades of tuning that cannot be recreated in a release cycle. Inference tolerates immature software far better than multi-week training runs do, which is exactly why the benchmark pattern reported in the field splits along that line.

05 Export Controls as a Forcing Function

Export controls have shaped this market at every stage. The restrictions began with the A100 and H100 ban in October 2022 and tightened in October 2023. The 2025 allow-then-restrict cycle around the H20 then taught Chinese buyers a specific lesson: access to NVIDIA silicon is a policy variable, not a supply relationship, and a procurement strategy built on it can be revoked with a letter.

The commercial consequence was immediate. Orders that once went to imported accelerators moved to domestic alternatives, giving Huawei a guaranteed demand base and the revenue to keep iterating through yield problems that would sink an unbacked product line. Sanctions designed to slow the domestic stack have, in the narrow sense of purchase volume, accelerated it - a tradeoff policymakers are still working through.

06 What Independent Benchmarks Actually Show

Public head-to-head benchmarks remain scarce, and many that surface come from operators with a stake in the answer. The consistent pattern in credible reporting: the 910C is competitive for inference workloads, where throughput per dollar matters more than peak floating-point, and considerably harder to recommend for frontier-scale training, where interconnect quality and software maturity compound over weeks of uninterrupted execution.

Power per token is the tax on the workaround. Huawei compensates weaker per-chip interconnect with scale - CloudMatrix 384 systems network 384 Ascend chips against the 72 GPUs of an NVIDIA GB200 NVL72 rack - and that compensation is paid on the electricity bill. A stack that needs roughly four times the units to do comparable work consumes a multiple of the power to do it, and at datacenter scale that line item decides the economics.

07 The Capacity Math That Decides the Gap

The gap, then, is a product of four multiplied terms: units shipped, yield per wafer, interconnect quality, and software maturity. They compound rather than add, so weakness in one term can be offset by strength in another only up to a point. Huawei's strategy is explicit: over-invest in units and system scale while the yield and software terms mature behind them, and let guaranteed domestic demand carry the cost of that transition.

The measured conclusion sits between the clickbait and the dismissal. The 910C is not garbage - it is a working accelerator produced under sanction, good enough for inference at scale today, with a training story that is behind and power-hungry but improving. The two-generation deficit closes architecture by architecture, and the arithmetic of units, yields, interconnect, and software - not a video title - decides how fast.