Inside a 2-Nanometer Chip Fab: How Microchips Are Fabricated at Nanoscale

01 Start with a Perfect Wafer

Fabrication begins with ultra-pure silicon refined into a single crystal and sliced into wafers. The surface is polished until microscopic roughness is small compared with the structures engineers intend to print.

A wafer is not a finished chip. It is a platform on which dozens of repeated layers will be built, tested, and eventually divided into individual dies.

02 Lithography Draws the Pattern

Photolithography coats the wafer with a light-sensitive resist. A mask or projection system exposes selected regions, creating a temporary pattern that defines where material will be removed or added.

Extreme ultraviolet lithography uses 13.5-nanometer light for some leading-edge layers. Resolution is not simply the wavelength: optics, resist chemistry, focus, vibration, and computational correction all matter.

03 Deposition and Etch

Thin films of insulators, conductors, and semiconductors are deposited across the wafer. Etching then removes selected areas, transferring the pattern into the layer below.

The process is repeated many times. Each cycle adds another part of the transistor, interconnect, isolation structure, or contact. A defect in one layer can ruin the device beneath it.

04 Doping Creates Electrical Behavior

Ion implantation introduces carefully controlled impurities into silicon. These dopants change the concentration and type of charge carriers, creating the source, drain, and channel regions that let a transistor switch.

Modern gate-all-around and FinFET structures use three-dimensional geometry to improve control of the channel. The label “2 nanometer” describes a process generation, not a ruler measurement of every feature.

05 Inspection Is Part of the Build

Metrology tools measure line width, overlay, film thickness, defect density, and electrical behavior. Inspection is performed throughout the flow because waiting until the end would waste weeks of processing.

Yield is the fraction of dies that meet specifications. Better yield comes from cleaner materials, tighter process control, defect learning, and designs that tolerate some variation.

06 From Wafer to System

After front-end fabrication, the wafer is electrically tested and diced. Dies are packaged with substrates, interconnects, heat spreaders, and sometimes multiple chiplets. Packaging increasingly determines bandwidth, power delivery, and total system performance.

The finished processor is therefore the product of an ecosystem: semiconductor chemistry, precision machinery, software design, packaging, testing, and a supply chain that must keep every step synchronized.