Intel Core Ultra: The Chiplet Remaking the PC

01The End of the Monolithic Laptop Chip

For most of the modern PC era, a laptop processor was one piece of silicon: a single die, manufactured as a whole, with every function etched into the same rectangular slab of silicon. On December 14, 2023, Intel officially abandoned that tradition. Meteor Lake, the codename for its Core Ultra Series 1 mobile processors, was released that day, and per Wikipedia it is the first generation of Intel mobile processors to use a chiplet architecture, which means the processor is a multi-chip module: an assembly of several separately manufactured dies that behave, to the software running on them, like one chip. The design effort was led by Tim Wilson, according to the same source.

The rebrand matters as much as the packaging. Intel Core, as Wikipedia summarizes it, is the company's line of multi-core central processing units aimed at midrange, embedded, workstation, high-end, enthusiast, gaming, and entry-level server markets, the family that displaced Pentium from the mid-to-high-end and pushed it into the budget tier. Core Ultra now sits at the top of that family, and the "Ultra" label is not a marketing garnish so much as a demarcation line: new packaging, new core designs, new process technology, and for the first time in an Intel client processor, silicon dedicated specifically to artificial intelligence.

Why break a monolithic chip apart at all? The honest answer is economics. A large die manufactured on a new process node has a worse yield than several smaller dies, because a single defect anywhere on a big slab can spoil the whole thing, while several small dies mean a defect spoils only one tile, which can be sorted out before assembly. Chiplets also let Intel mix process nodes in one product, putting only the performance-critical logic on its newest and most expensive manufacturing process. And tiles designed and validated independently can be refreshed independently, which shortens iteration cycles. These are structural arguments, not benchmarks, but they explain why the whole industry, not just Intel, has moved this direction.

02Four Tiles, One Package

Meteor Lake is assembled from four active tiles stacked and connected through Foveros, Intel's 3D packaging technology, which bonds dies face-to-face with dense electrical connections so signals cross between tiles almost as if they were on the same silicon. Per Intel's published architecture disclosures, the four tiles divide the work as follows: a compute tile carries the performance and efficiency cores; a SoC tile carries the low-power cores, the memory controllers, media engines, and the NPU; a graphics tile carries the Arc integrated GPU; and an IO tile handles the peripheral interfaces. A passive base die sits beneath the active tiles and routes power and signals between them.

The node assignments are the quietly radical part. The compute tile is built on Intel 4, the company's first deployment of its EUV-class manufacturing process, while the media-rich SoC tile and the IO tile use TSMC's N6, a mature and cheaper node, and the graphics tile uses TSMC's N5. Intel publicly disclosed those assignments at launch, and they matter because they show the architecture doing what chiplets are supposed to do: buy the newest, most expensive transistors only where they pay for themselves in performance, and use cheaper ones everywhere else. That is a measured, published fact about the product, and it is the strongest single piece of evidence that the chiplet pivot is an economic strategy rather than a technical stunt.

There is a trade-off, and it is worth stating plainly: signals crossing between tiles are not free. Inter-die links add latency and design complexity compared with one homogeneous die, and a multi-chip module must be tuned so the seams do not show up in software. Analysis suggests the gains in manufacturing flexibility outweighed the interconnect penalty for Intel's mobile goals, where power efficiency and area economics dominate, but a monolithic design retains advantages in latency-sensitive segments. The chiplet bet is a judgment call about which costs matter, and Meteor Lake is that judgment made silicon.

03Three Kinds of Cores in One Chip

The compute tile pairs two core designs: Redwood Cove performance cores (Intel's P-cores) for heavy single-threaded work, and Crestmont efficient cores (E-cores) for throughput and background tasks. Nothing there is new in principle; Intel had shipped hybrid P-core and E-core designs since the 12th-generation Alder Lake family. What Meteor Lake adds is a third tier, and it lives in a different place entirely: low-power efficient cores (LP-E cores) on the SoC tile, physically separated from the big compute tile, able to run without powering the compute tile up at all.

That separation is the architecture's battery pitch. Audio playback, system housekeeping, synchronization jobs, and app background maintenance are exactly the kind of lightweight but persistent workloads that historically kept a laptop's main compute silicon awake. On Meteor Lake, the Thread Director, Intel's hardware scheduler, can steer those threads onto the LP-E island and leave the performance cores dark. Intel's launch materials claimed meaningful power savings from this arrangement for exactly those scenarios, and while vendor power claims deserve independent verification, the structural argument is sound: the cheapest watt is the one you never draw.

The result is a processor that is really a federation of specialists, coordinated by scheduling hardware rather than fused by proximity. That has consequences for how software must be written and tuned, since a thread placed on the wrong tier of the hierarchy can cost battery or performance disproportionate to its importance. It also foreshadows the NPU, which takes the same idea, a dedicated engine for a specific class of work, and pushes it further.

04The NPU and the TOPS Race

The headline feature of the SoC tile is the neural processing unit, branded AI Boost by Intel: a fixed-function accelerator designed for sustained, low-power machine learning inference rather than the bursty heavy lifting of a CPU or GPU. In its December 2023 launch materials, Intel put Meteor Lake's total AI throughput at about 34 TOPS across the platform, split roughly as 5 TOPS from the CPU cores, 18 TOPS from the integrated Arc GPU, and 11 TOPS from the NPU itself. TOPS means trillions of operations per second, and the chart below shows that split as Intel presented it.

It is worth being precise about what TOPS does and does not tell you, because the unit became the marketing currency of the AI PC era overnight. TOPS counts arithmetic operations per second at a stated precision, typically INT8, and says nothing about memory bandwidth, cache behavior, what fraction of peak a real workload sustains, or how much power the engine draws while doing it. Two chips with identical TOPS figures can differ enormously in delivered performance, which is why the number belongs in the spec sheet and not on the scoreboard. Treat it as a capacity statement, not a benchmark result.

So why add an NPU when the GPU already out-TOPS it in Intel's own figures? The answer is efficiency under sustained load. A general-purpose GPU is extraordinarily fast but draws watts to be that way, which is fine for a few seconds of video effects and poor for a camera filter that runs for an hour. The NPU is sized for continuous, low-power inference: background segmentation, noise suppression, transcription, the small always-on models that a modern laptop runs without the user ever noticing. That division of labor, burst on the GPU, sustained on the NPU, is the actual design thesis of the AI PC, and TOPS alone cannot capture it.

05Series 1, Series 2, and the Copilot+ Bar

The naming scheme is easier to read than it looks. "Core Ultra" is the tier; the digit after Ultra, 5, 7, or 9, is the segmentation within the tier, roughly the same as before; and the Series number is the generation family. Meteor Lake is Series 1, launched December 2023. Lunar Lake, the follow-up mobile generation launched in September 2024, is Series 2, and its NPU, marketed as NPU 4, is rated by Intel at up to 48 TOPS on its own, more than four times Meteor Lake's NPU figure. The desktop got its own Core Ultra, the Series 2 family launched in late 2024, whose NPU is rated at 13 TOPS.

That generational ladder is the story of the AI PC in one picture, and the middle bar explains why. In May 2024, Microsoft defined the Copilot+ PC category and required at least 40 TOPS of NPU throughput to qualify. Meteor Lake's 11 TOPS NPU falls well below that bar, so the very first generation of "AI PCs" was excluded from the flagship AI branding within about five months of its launch. That is a measured fact, not an interpretation, and buyers of first-generation Core Ultra hardware lived it. The 40 TOPS figure is a vendor category threshold rather than a demonstrated capability boundary, but category definitions set software support, and software support is what an NPU is for.

Analysis suggests the lesson is about the definition moving faster than the product cycle. The AI PC was branded, specified, rebranded, and re-specified in the space of two years, and TOPS, for all its flaws as a metric, was the currency in which that argument was conducted. Anyone shopping this generation of hardware should assume the bar will move again.

06What On-Device AI Actually Runs

Strip the marketing away and the question is simple: what does the NPU actually do on a real machine? The concrete, shipped answers so far are modest and mostly sensory: Windows Studio Effects for background blur, automatic framing, and eye contact during video calls; live captions and real-time translation; voice clarity and noise suppression; local media indexing and search; and a growing set of small local models that the operating system vendors route to the NPU for efficiency. These are real workloads with real power savings, and they are continuous, small, and latency-sensitive, which is precisely the envelope the NPU was sized for.

What does not run locally is the headline AI: the frontier chatbots that drive public perception of the technology are trained datacenter models, orders of magnitude too large for a laptop NPU or its memory. Local inference today means small, distilled, task-specific models doing bounded jobs, with the cloud still doing the heavy lifting for general intelligence. Analysis suggests the honest framing is that the NPU is currently an efficiency play, not an intelligence play: it exists to move a class of inference workloads off the cloud and off the power-hungry GPU, not to make the laptop itself smart in the way the advertising implies.

That is not a dismissal. Meteor Lake's architecture is a genuine break: the first tiled client processor, the first client NPU, and the template for every Core Ultra generation since. The tile decomposition survived into subsequent generations, the NPU became a fixture, and the multi-chip module that began as a manufacturing compromise is now the assumed shape of a PC processor. The verdict on the AI PC, as opposed to the architecture, will be written by software: by whether developers build for the NPU in numbers that make the 40 TOPS worth paying for. Judge the chip by what runs on it, not by the sticker.