The End of Moore's Law: How Transistors Are Approaching Atomic Limits

01 The Observation That Became a Law

In 1965, Gordon Moore -- then director of research at Fairchild Semiconductor -- published a short paper in Electronics Magazine noting that the number of components per integrated circuit had doubled roughly every year, and he predicted this trend would continue for at least a decade. A decade later, the doubling period had eased to about two years, and the semiconductor industry had organized itself around meeting what was now called Moore's Law as though it were a physical mandate rather than an empirical observation.

Moore himself called it a extrapolation, not a law of nature. Yet the prediction proved remarkably durable. For five decades, foundries, design houses, and equipment makers coordinated massive capital investments around the shared assumption that each generation would pack roughly twice the transistors into the same area. That coordination function -- a shared roadmap that aligned suppliers, manufacturers, and customers -- may have been more important than any single lithographic breakthrough.

The economic logic was straightforward: smaller transistors switch faster, consume less power per operation, and cost less per transistor when produced at scale. Each node shrink delivered more performance per dollar, which drove demand, which funded the next round of research and fabrication equipment. The flywheel spun for half a century.

02 The Scaling Engine and Its Friction

Classical MOSFET scaling, formalized by Robert Dennard in 1974, prescribed that as transistor dimensions shrank by a factor k, the operating voltage and current should scale by the same factor, keeping the electric field constant. This Dennard scaling meant each generation delivered more performance at lower power -- the combination that made modern mobile computing possible.

Dennard scaling broke down around the mid-2000s, when supply voltages could not be reduced further without degrading switching speed and leakage. Transistors kept getting smaller, but they no longer automatically got more energy-efficient. The industry responded by building multi-core processors rather than pushing single-thread clock speeds, and by investing heavily in power-management techniques that gate clocks and voltages dynamically.

Moore's Law itself -- the transistor-density trend -- outlived Dennard scaling by nearly two decades, but the decoupling of density from efficiency was the first crack. It meant that simply shrinking features was no longer enough; architectural innovation became equally important.

03 Lithography at the Frontier: DUV to EUV

The tool that made Moore's Law physically possible is the photolithography scanner, which projects a patterned light beam through a mask onto a silicon wafer coated with photoresist. The minimum feature size is governed by the wavelength of light used. For decades, the industry used deep ultraviolet (DUV) light at 193nm wavelength, combined with clever multi-patterning techniques, to push features down to 14nm and even 10nm.

EUV lithography, using 13.5nm extreme ultraviolet light, was first deployed in commercial production by ASML around 2018 for the 7nm node. The technology was staggeringly difficult to develop: EUV light is absorbed by nearly all matter, including air, so the entire optical path must operate in vacuum, and the light itself is generated by shooting microscopic droplets of tin with a high-power laser -- twice -- to create a plasma that emits at the right wavelength.

A single EUV scanner costs more than $200 million and occupies the footprint of a school bus. Only ASML produces them, and only three companies -- TSMC, Samsung, and Intel -- operate them at the leading edge. The capital intensity has thinned the field of leading-edge foundries from dozens in the 1990s to effectively three today.

04 Quantum Tunneling and the Atomic Wall

As transistor gate lengths approach the single-digit nanometer range, they enter a regime where quantum mechanical effects dominate. The gate oxide -- the insulating layer that controls current flow between source and drain -- has been only a few atoms thick for several generations. At this thickness, quantum tunneling allows electrons to leak through the barrier even when the transistor is nominally off.

Leakage current means wasted power and heat. At the 5nm and 3nm nodes, foundries report that static power consumption from leakage can rival dynamic power under certain workloads. The conventional planar MOSFET, which served the industry from the 1960s through the 2010s, became impractical below 22nm because the gate could no longer effectively control the channel.

The atomic limit is not a cliff but a slope. Silicon atoms are about 0.2nm in diameter, so a 2nm feature is only about ten atoms across. Manufacturing tolerances, doping uniformity, and contact resistance all become progressively harder to control. The question is not whether scaling stops, but when the cost of each additional shrink exceeds the benefit.

05 New Architectures: FinFET, GAA, and Beyond

The industry's first structural answer to the planar limit was the FinFET, a three-dimensional transistor geometry in which the channel rises as a fin above the substrate and the gate wraps around three sides. Intel introduced FinFETs at the 22nm node in 2012; TSMC and Samsung followed at 16nm and 14nm. FinFETs restored gate control by increasing the surface area between the gate and the channel.

FinFETs are now giving way to Gate-All-Around (GAA) transistors, where the channel is a nanosheet surrounded on all four sides by the gate. Samsung introduced GAA at 3nm in 2022; TSMC adopted a similar structure (called NCFET) at 2nm in 2025. GAA provides even better electrostatic control, but it is significantly more complex to manufacture, requiring precise etching of stacked nanosheets.

These architectural changes buy time -- perhaps two or three additional nodes -- but they do not change the fundamental scaling trajectory. Each structural innovation extends the curve by making the transistor harder to build, not by changing the physics that will eventually halt it.

06 3D Stacking, Chiplets, and the Packaging Revolution

As lateral scaling becomes prohibitively expensive, the industry has pivoted toward vertical integration -- stacking multiple silicon dies on top of each other or side by side within a single package. TSMC's CoWoS (Chip-on-Wafer-on-Substrate) and SoIC (System on Integrated Chips) technologies allow logic, memory, and I/O dies to be bonded face-to-face with micrometer-scale interconnects.

The chiplet approach decomposes a large monolithic die into smaller, specialized dies that are fabricated on the process node best suited to each function: leading-edge nodes for compute, older cheaper nodes for I/O and analog. AMD's Ryzen and EPYC processors have used chiplets since 2017, and Intel's Ponte Vecchio and Meteor Lake followed suit. The UCIe (Universal Chiplet Interconnect Express) standard, introduced in 2022, aims to make chiplets from different vendors interoperable.

Packaging innovation has become the primary path for continued system-level performance gains, even as individual transistor scaling slows. The economic logic is compelling: a 600mm monolithic die on 3nm costs far more and yields worse than four 150mm chiplets bonded together with comparable aggregate performance.

07 Beyond Silicon: What Comes After Moore

Several post-silicon candidates are under active investigation. Carbon nanotube transistors (CNFETs) offer higher carrier mobility and smaller footprints than silicon, but manufacturing them at scale remains a formidable challenge -- no foundry has yet demonstrated CNFET production at commercial volumes. 2D materials such as molybdenum disulfide (MoS2) offer atomically thin channels that could in principle scale below 1nm, but the same fabrication difficulties apply.

Neuromorphic and analog computing architectures, which trade exact digital precision for massive parallelism and energy efficiency, are being explored for specific workloads like inference and signal processing. IBM's TrueNorth, Intel's Loihi, and various research chips demonstrate the concept, but none have displaced conventional digital silicon for general-purpose computing.

Quantum computing, while fundamentally different from classical scaling, is often invoked in Moore's Law obituaries. Quantum processors do not extend the transistor-density curve; they address a different class of problems. For the foreseeable future, classical silicon -- augmented by advanced packaging, domain-specific accelerators, and increasingly sophisticated power management -- remains the foundation of computing infrastructure.

The end of Moore's Law, when it arrives, will not be a technological event but an economic one: the point at which the cost of shrinking a node exceeds the value of the transistors gained. The industry may be approaching that inflection, but the history of premature obituaries suggests caution. What is certain is that the next decade of computing progress will come as much from architecture and packaging as from lithography.