NVIDIA's Rubin platform: six chips, one AI supercomputer

01 GTC 2026: the Rubin platform unveiled

At its GTC conference, NVIDIA — the Santa Clara-based company whose GPUs have become the default substrate of modern AI — formally laid out Rubin as the successor platform to Blackwell, the GPU microarchitecture that has anchored its data-center line since 2024. The framing was deliberate: Rubin is not "a faster chip" but a platform, a coordinated family of six new chips spanning processors, GPUs, and the interconnect fabric that binds them, designed from the first sketch to operate as a single machine.

The history here is one of accelerating cadence. Hopper, introduced in 2022, established the template of data-center GPUs built alongside consumer architectures; Blackwell compressed the follow-up to roughly two years. Rubin lands on the same rhythm — and, notably, the company now brands the platform with a CPU-and-GPU pairing ("Vera Rubin") rather than leading with the GPU alone. That naming shift is itself information: when the processor and the accelerator are co-designed and co-launched, the product is the combination.

02 The six chips and what each does

The "six chips" formulation is best read as an org chart for a rack. The roles, per NVIDIA's platform materials and the video's walkthrough: a Vera CPU built on the company's in-house server processor design for general orchestration; Rubin GPUs for the matrix math that dominates model training and inference; HBM4 memory stacks feeding those GPUs at higher bandwidth than the HBM3e generation used by Blackwell; NVLink 6, the chip-to-chip interconnect that lets GPUs pool memory and act in concert; NVSwitch silicon that wires hundreds of chips into one switched fabric; and BlueField networking for the data-center-scale input and output. Each is replaceable in isolation; the point is that together they are sold as one system.

Why bundle? Because AI workloads are communication-bound as often as they are compute-bound. When a model is too large for one GPU's memory — and frontier models long since crossed that line — the speed of the links between chips becomes as decisive as the chips themselves. A platform vendor who controls the processor, the accelerator, the memory roadmap, and the wire between them can optimize all four at once. The trade-off, which section six returns to, is that customers buying the whole bundle deepen their dependence on a single supplier.

03 Vera Rubin architecture vs Blackwell: the performance leap

On raw paper specs, the generational jump is substantial. Blackwell's headline inference figure, as announced at GTC 2024, was on the order of 20 petaflops of FP4 throughput per GPU package — FP4 being a four-bit floating-point format that trades precision for throughput, a trade the industry has embraced for inference workloads. Rubin's announced FP4 figure is roughly two and a half times that, paired with a move from HBM3e to HBM4 memory, lifting memory bandwidth — the rate at which data reaches the compute cores — by a similar proportion. These are manufacturer-announced figures, not independently measured ones; the chart below should be read in that register.

Two caveats keep the interpretation honest. First, announced petaflops describe a ceiling under ideal conditions; real training and inference runs depend on memory locality, network contention, and software maturity, which is why the Hopper-to-Blackwell transition took months of firmware and kernel tuning to deliver its promised throughput. Second, the leap that may matter most is architectural rather than arithmetic: pairing a purpose-built CPU with the GPU on a unified memory fabric reduces the data shuffling that has historically eaten a meaningful share of cluster time. NVIDIA's own positioning, echoed in its video materials, is that rack-level output per rack — not chip-level peaks — is the metric Rubin is engineered to move.

04 Rack-scale computing and NVL144

NVL144 is the shipping form of that argument. The name describes a rack — the standard steel frame that holds data-center hardware — in which 144 GPU dies behave, from the software's perspective, as one accelerator with one enormous shared memory. The dies are fused by NVLink and NVSwitch into a single coherent domain, so a model that would normally be split, with all the scheduling overhead that implies, can instead be treated as resident on one machine. This is the "one AI supercomputer" of the headline: not a row of separate boxes, but a cabinet that ships, plugs in, and functions as a unit.

The economic logic follows. Historically, buyers assembled capacity from parts — GPUs, switches, cables, and the engineering hours to make them cooperate. Rack-scale products collapse that integration work into the factory, which is why NVIDIA prices and sells these systems per rack rather than per chip. For hyperscale buyers the calculus is throughput per square meter and per megawatt; for smaller buyers, the rise of rack-scale rentals through cloud providers means the supercomputer is becoming something one leases by the hour rather than constructs. The measured claim here is deployment speed; the interpretive claim, well supported by the last two product cycles, is that integration is now the product.

05 Power, cooling, and data-center economics

Rubin's performance numbers arrive with an invoice attached. Each generation of flagship GPUs has pushed per-rack power draw upward — Blackwell-class racks already run in the vicinity of 100-120 kilowatts, and Rubin-class systems are designed for higher still, which pushes the industry decisively toward liquid cooling: pumping coolant directly past the hottest components because air can no longer move enough heat at acceptable energy cost. Data centers are measured in PUE — power usage effectiveness, the ratio of total facility power to power that reaches the computers — and cooling is the main lever on that ratio.

The economic story is two-sided. On one side, performance per watt — the honest measure of AI efficiency — has improved every generation, so the cost per token of AI output keeps falling. On the other, absolute facility power is growing fast enough that grid connection queues, on-site generation, and utility negotiations are now board-level concerns for the buyers of these systems. Our interpretation: at this scale, NVIDIA is no longer competing only against other chipmakers but against the physics of the electrical grid, and the platform that pairs top throughput with manageable kilowatts wins the deals that silicon specs alone would lose.

06 Competitive field: AMD, custom silicon, hyperscalers

Rubin launches into a market with three distinct kinds of challengers. AMD's Instinct accelerators compete directly on specifications and offer a second source for buyers wary of single-vendor pricing; its coupling to open software ecosystems is the pitch where it most differs from NVIDIA's proprietary stack. The hyperscalers — the largest cloud operators — design their own training chips in-house, aimed squarely at the internal workloads where they control the software; these chips rarely challenge NVIDIA on general-purpose capability but erode its volume at the margins. And a field of startup silicon targets inference specifically, where specialized designs can beat general ones on cost per output token.

NVIDIA's defense is the platform itself. The six-chip bundle — processor, accelerator, memory roadmap, interconnect, switch, networking — is only partly about performance; it is also about making the integrated option the path of least resistance. The company's CUDA software ecosystem, now nearly two decades of accumulated libraries and tooling, remains the strongest switching cost in enterprise computing. The open question, which no keynote answers, is whether integration compounds into durable advantage or into the kind of dependency that regulators and large customers eventually push back against. Both readings of the same fact are currently in circulation, and both are honest.

07 Supply chain and what Rubin means for 2026-2027

The constraint on Rubin's first years is not demand — it is the supply chain beneath the platform. Advanced packaging capacity, HBM4 memory allocation, and leading-edge wafer fabrication are all contended resources, and every AI vendor draws on the same foundries and memory makers. Allocation decisions made a year before launch determine who can ship racks in volume, which is why NVIDIA's customer list reads like a who's-who of companies that pre-purchased capacity. CoPackers, substrate suppliers, and cooling-component vendors form the long tail of bottlenecks that headlines rarely name but deployment schedules feel.

For 2026-2027, three things seem most worth watching. First, whether Rubin's rack-level throughput claims survive contact with production clusters — the interval between keynote and reality has historically been measured in quarters. Second, whether HBM4 supply constrains volume, and what that does to pricing power up and down the stack. Third, whether the competitive field's alternatives mature from viable to compelling, giving large buyers real leverage for the first time in this cycle. The platform's significance is already clear regardless: the AI supercomputer is no longer a place you go — it is a product you order, and NVIDIA just defined its next unit.