Vera Rubin vs Helios: The AI Chip War Enters Its Next Phase

01 The Blackwell Inheritance

Nvidia's Blackwell architecture, introduced in late 2024 with the B200 and GB200 systems, represents the current state of the art in AI training hardware. The B200 GPU delivers approximately 9,000 FP8 TFLOPS of peak compute, roughly 2.3 times the FP8 throughput of its predecessor, the Hopper-based H100. The performance gain comes from a combination of die size increase, process node advancement from TSMC's 4N to 4NP, and the introduction of second-generation Transformer Engine hardware that accelerates attention computation natively.

The GB200 system, which pairs two B200 GPUs with a Grace CPU in a single rack-scale module, demonstrated the economics that have made Nvidia dominant. A single GB200 NVL72 rack, containing 72 B200 GPUs interconnected via NVLink, delivers approximately 1.4 exaFLOPS of AI compute at a power draw of 120 kilowatts. The price per rack exceeds $3 million, but the cost per training token drops by approximately 40% compared to H100-based systems, making it the cheapest path to frontier-model training despite the sticker price.

What Blackwell did not solve was the memory wall. HBM3e memory on the B200 provides 8 TB/s of bandwidth per GPU, but the ratio of memory bandwidth to compute has been declining since the H100. This means that for memory-bound workloads, which include most large-language-model inference, the B200's advantage over the H100 is smaller than the raw FLOPS numbers suggest. Vera Rubin's architecture is designed to address this gap.

02 What Vera Rubin Changes

Nvidia announced the Vera Rubin GPU at GTC 2026, naming it after the astronomer who discovered evidence of dark matter. The architecture represents a generational shift on three axes: process node, memory technology, and interconnect. Vera Rubin is fabricated on TSMC's 2-nanometer process, the first Nvidia GPU to use the node, which delivers approximately 15% performance improvement and 30% power reduction compared to the 4NP node used for Blackwell. The die size is expected to be similar to the B200, meaning the transistor count increase is proportional to the density gain.

The more significant change is the adoption of HBM4 memory. HBM4 doubles the number of memory channels from 8 to 16 per stack, and the per-stack capacity increases from 24 GB to 36 GB. With four stacks per GPU, total memory capacity rises to 144 GB and bandwidth to approximately 12 TB/s. This represents a 50% bandwidth increase over the B200's 8 TB/s, which narrows the compute-to-memory ratio gap. For inference workloads, this is the improvement that matters most: it means larger models can be served from a single GPU without tensor parallelism across multiple devices.

The interconnect story is the third pillar. Vera Rubin introduces the next generation of NVLink, which increases per-GPU bandwidth from 1.8 TB/s to 3.6 TB/s. This enables larger all-reduce operations in distributed training with lower latency, and it makes rack-scale systems with 72 or more GPUs more efficient for models that exceed the memory capacity of a single device. The Rubin NVL72 system, mirroring the GB200 NVL72, is expected to deliver approximately 3.6 exaFLOPS of FP8 compute, 2.5 times the GB200, at a rack power draw estimated at 180 kilowatts.

03 AMD Enters the Ring

AMD's Helios system, revealed in an exclusive CNBC preview, is the company's most serious attempt to challenge Nvidia in the AI training market. Helios is a rack-scale system built around the MI400 series GPU, which is fabricated on TSMC's 3-nanometer process and uses HBM3e memory. The MI400 is expected to deliver approximately 12,000 FP8 TFLOPS, which is below Vera Rubin's estimated 18,000 but above the B200's 9,000. The competitive positioning is clear: Helios targets the gap between Blackwell and Rubin, offering better-than-Blackwell performance at a lower price than Rubin.

AMD's advantage is in the system integration. The Helios rack combines MI400 GPUs with AMD's own EPYC CPU and Instinct networking, all managed by a unified ROCm software stack. This contrasts with Nvidia's approach of sourcing networking from its Mellanox acquisition and CPUs from its Grace design. AMD's vertical integration means fewer vendor relationships for datacenter operators, and it allows AMD to optimize the full stack from chip to rack without cross-company coordination overhead.

The weakness remains software. ROCm, AMD's compute platform, has improved significantly with version 6.x, achieving near-feature-parity with CUDA for PyTorch and JAX workloads. But the ecosystem gap is not just about framework support; it is about the millions of lines of CUDA code that exist in production training pipelines, custom kernels, and inference engines. Porting that code to ROCm is non-trivial, and until there is a compelling economic reason to do so, the default path for new AI projects will remain Nvidia. Helios's success depends on whether the price-performance advantage is large enough to justify the migration cost.

04 The Memory Wall

HBM4 is the most critical component in both Vera Rubin and AMD's next-generation GPUs, and it is also the most supply-constrained. High Bandwidth Memory is manufactured by only three companies: SK Hynix, Samsung, and Micron. SK Hynix currently holds approximately 55% of HBM market share, Samsung approximately 35%, and Micron the remainder. The production capacity for HBM4, which requires more advanced through-silicon via (TSV) technology than HBM3e, is expected to be constrained through 2027.

The constraint matters because HBM is the component that determines how many GPUs can actually be built. Nvidia and AMD can design chips, but if the HBM supply is insufficient, they cannot ship them. TSMC's 2nm process has its own capacity constraints, but the HBM bottleneck is tighter because it requires coordination between memory manufacturers, foundries, and GPU designers across multiple packaging steps. The HBM4 supply allocation for 2026 is already committed, with Nvidia securing the majority of SK Hynix's initial production.

The implication for competition is significant. AMD's Helios system will ship with HBM3e rather than HBM4 in its initial generation, because HBM4 supply will be insufficient to serve both Nvidia and AMD at full volume. This means AMD's memory bandwidth advantage over the B200 is modest, and the gap versus Vera Rubin will be substantial. The HBM supply chain, not the GPU architecture, may be the factor that determines market share in the next generation of AI hardware.

05 Power and Cooling

The power consumption of AI training racks has become a defining constraint. The H100 rack drew 42 kilowatts; the B200 rack draws 120 kW; Vera Rubin is estimated at 180 kW. For context, a typical US household draws approximately 1.2 kW on average. A single Vera Rubin rack draws the power of 150 homes. At this power density, air cooling is no longer viable, and direct-to-chip liquid cooling is mandatory.

The cooling infrastructure requirement is where the AI chip war intersects with physical infrastructure. A datacenter designed for H100 racks can be retrofitted for B200 with moderate modifications: upgraded power distribution and rear-door heat exchangers. A datacenter designed for B200 cannot serve Vera Rubin without a full liquid cooling retrofit, which costs approximately $5 million per megawatt of IT capacity. This creates a natural upgrade cycle: hyperscalers who invested in B200 infrastructure in 2025 will be reluctant to write it off for Vera Rubin in 2026, potentially slowing Rubin adoption.

AMD's Helios, at an estimated 150 kW per rack, sits between B200 and Vera Rubin in power draw. This positioning may be intentional: it allows Helios to be deployed in datacenters built for B200 with moderate cooling upgrades, avoiding the full liquid-cooling requirement that Vera Rubin imposes. If AMD's price-performance is competitive, the lower infrastructure cost could be a meaningful selling point for hyperscalers who are not ready to build greenfield liquid-cooled facilities.

06 The Software Moat

Nvidia's dominance in AI training is often attributed to hardware, but the more durable advantage is CUDA. The CUDA ecosystem, built over 18 years, includes the cuDNN library, the NCCL collective communications library, the Triton inference server, and thousands of community-contributed kernels. Every major deep learning framework, PyTorch, JAX, and TensorFlow, defaults to CUDA. This is not a marketing advantage; it is a switching cost. Moving a production training pipeline from CUDA to ROCm requires testing, debugging, and re-optimizing kernels that may have been tuned over years.

AMD's ROCm 6 has made significant progress. The HIP programming model, which provides a CUDA-like API, can compile many CUDA programs with minimal modification. PyTorch 2.x includes native ROCm backends, and AMD has invested in OpenAI's Triton language, which provides a vendor-neutral path for writing GPU kernels. The Triton route is the most promising path to breaking the CUDA lock-in, because it abstracts the hardware target and allows the same kernel code to run on both Nvidia and AMD GPUs.

But the ecosystem gap is not just about frameworks. It is about the long tail of custom kernels, optimization tricks, and institutional knowledge that exists in CUDA. When a training run fails at 3 AM, the engineer who debugs it reaches for CUDA documentation, CUDA profilers, and CUDA community forums. That institutional knowledge does not transfer overnight. AMD's strategy is to narrow the gap incrementally, but the moat is deep, and the most likely outcome is a multi-year convergence rather than a sudden breakthrough.

07 What the Chip War Means

The competition between Nvidia's Vera Rubin and AMD's Helios is not just a commercial rivalry. It is a component of national AI policy. The US government's export controls on advanced AI chips, first imposed in October 2022 and tightened repeatedly since, are designed to maintain a compute gap between the US and its strategic competitors, particularly China. The CHIPS and Science Act, which provides $52 billion in semiconductor manufacturing subsidies, is the supply-side counterpart: it aims to ensure that the most advanced chips are fabricated in the US or in allied countries.

TSMC's 2nm process, on which Vera Rubin depends, is currently produced only in Taiwan. TSMC's Arizona fabs, which began 4nm production in 2025, are scheduled to begin 2nm production in 2027. This means that the most advanced AI GPUs will be fabricated in Taiwan for at least another year, a geographic concentration that represents a strategic vulnerability. AMD's MI400, fabricated on TSMC's 3nm process, is in the same position. The chip war, for all its commercial dimension, is ultimately about whether the physical manufacturing of AI compute can be distributed across geographies that are not exposed to a single choke point.

For the AI industry, the practical implication is that the next generation of training hardware will be more expensive, more power-hungry, and more supply-constrained than the current one. The performance gains are real, but they come with infrastructure costs that only hyperscalers can absorb. The gap between the companies that can afford to build frontier-model training clusters and those that cannot is widening, and the chip war, in both its commercial and geopolitical dimensions, is the mechanism by which that gap is maintained.