From Sand to Silicon: How Microchips Are Made

Figure 1: Transistor count per chip has followed Moore's Law, roughly doubling every two years from the Intel 4004 (2,300 transistors, 1971) to modern GPUs exceeding 80 billion.

01 The Raw Material: From Quartz to Purified Silicon

The journey begins with quartzite, a form of sand composed largely of silicon dioxide. Quartz is melted in a carbon arc furnace at approximately 1,900 degrees Celsius to produce metallurgical-grade silicon, which is about 98% pure. This silicon is then converted to trichlorosilane gas, distilled to remove impurities, and deposited onto a seed crystal in a process called the Czochralski method. A single crystal of silicon is slowly pulled from the melt, rotating as it grows, forming an ingot or boule that can be up to 300 millimeters in diameter and two meters long.

The resulting monocrystalline silicon is sliced into thin wafers, typically 0.7-0.9 millimeters thick, which are then polished to a mirror finish using chemical mechanical planarization. The surface flatness requirements are extraordinary: variations must be measured in nanometers. A single 300mm wafer can yield hundreds or thousands of individual chips depending on their size.

02 Photolithography: Printing Circuits with Light

The defining operation in chip manufacturing is photolithography, a process analogous to photography in which light transfers a circuit pattern from a mask onto the photosensitive surface of the wafer. A layer of photoresist is spin-coated onto the wafer, ultraviolet light is projected through a reticle containing the pattern, and the exposed photoresist is developed to reveal the underlying circuit structure.

The resolution of photolithography is governed by the wavelength of light used and the numerical aperture of the projection optics. For decades, the industry progressed by shrinking wavelengths: from 436nm (g-line) to 248nm (KrF excimer laser) to 193nm (ArF excimer laser). The transition to extreme ultraviolet (EUV) lithography at 13.5nm wavelength, commercialized by ASML starting in 2018, enabled the production of features below 10 nanometers and is essential for today's most advanced process nodes.

03 Etching, Doping, and Deposition

Once the photoresist pattern is in place, the wafer undergoes a series of material modification steps. Etching removes exposed material using either wet chemical baths or dry plasma etching, carving the circuit pattern into the underlying layers. Ion implantation shoots dopant atoms (boron, phosphorus, or arsenic) into the silicon to alter its electrical conductivity in specific regions, creating the n-type and p-type semiconductors that form transistors. Chemical vapor deposition and physical vapor deposition build up new layers of material, including insulating oxides and conductive metals.

A modern chip requires 30 to 80 of these lithography-etch-deposition cycles, building up billions of transistors layer by layer from the bottom of the wafer to the top. Each layer must be aligned to the previous one with nanometer precision. The entire process takes two to three months from raw wafer to finished chip, with each wafer traveling miles through the fab's automated material handling system.

Figure 2: The lithography-etch-deposition cycle repeats 30-80 times per wafer, building transistors layer by layer before final testing, dicing, and packaging.

04 Transistor Scaling and Moore's Law

Gordon Moore observed in 1965 that the number of transistors per integrated circuit doubled approximately every two years, a prediction that has held with remarkable fidelity for nearly six decades. This scaling has been achieved by shrinking transistor dimensions, enabled by successive generations of lithography. The Intel 4004 in 1971 contained 2,300 transistors at a 10 micrometer process node. Modern GPUs like NVIDIA's H100 contain over 80 billion transistors fabricated on TSMC's 4nm process.

The progression to smaller nodes has not been linear. The industry moved from planar transistors to FinFET (3D transistor) designs at the 22nm node around 2012, and to gate-all-around (GAA) transistors starting at the 3nm node. Each generation has required new materials, new lithography techniques, and increasingly complex multi-patterning schemes. The cost of developing a new process node has risen from roughly $1 million at the 1 micrometer generation to an estimated $1-2 billion for a 3nm-class process.

05 EUV Lithography: The Current Frontier

Extreme ultraviolet lithography represents the most significant advance in chipmaking technology in the past decade. EUV uses light at 13.5nm wavelength, more than ten times shorter than the 193nm argon fluoride lasers used in prior generations. This shorter wavelength directly enables smaller features without the costly multi-patterning steps that 193nm lithography required at advanced nodes.

Generating EUV light is itself an engineering marvel. An EUV source fires a high-power CO2 laser at microscopic droplets of molten tin, vaporizing each droplet twice to produce plasma that emits 13.5nm photons. This process repeats 50,000 times per second. The entire optical system must operate in a vacuum because air absorbs EUV light. Reflective mirrors coated with alternating layers of molybdenum and silicon are used instead of lenses, since no material is transparent at this wavelength. ASML remains the sole manufacturer of EUV lithography systems, with each machine costing $200-300 million.

06 The Economics of Semiconductor Fabs

The capital requirements for semiconductor manufacturing are staggering. A leading-edge fab costs $10-20 billion to build and contains the most expensive and precise equipment on Earth. A single EUV scanner costs more than a Boeing 747. The clean rooms where chips are made must maintain particle counts measured in particles per cubic meter, thousands of times cleaner than a hospital operating room, because a single dust particle can destroy a chip with features measured in single-digit nanometers.

This economic reality has driven industry consolidation. Only three companies -- TSMC, Samsung, and Intel -- currently operate leading-edge logic fabs at the most advanced nodes. TSMC alone produces roughly 60% of the world's chips manufactured at the most advanced process nodes. The strategic importance of semiconductor manufacturing has made it a focal point of industrial policy, with the US CHIPS Act, the EU Chips Act, and equivalent programs in Japan and South Korea collectively committing hundreds of billions of dollars to expand domestic fabrication capacity.

07 The Path to 2nm and Beyond

The industry's roadmap now points to the 2nm node, which entered risk production at TSMC in 2024. The transition from FinFET to gate-all-around (GAA) transistor architecture at this node represents a fundamental change in how transistors are structured, with the gate material surrounding the channel on all four sides to improve electrostatic control. Beyond 2nm, the industry is exploring complementary field-effect transistors (CFET), which stack n-type and p-type transistors vertically, and backside power delivery, which moves electrical connections to the bottom of the wafer to free space for signal routing on the top.

These innovations extend the frontier of Moore's Law, but each generation is harder and more expensive than the last. The question is not whether scaling will end -- it will, eventually -- but how much further the industry can push before the economics stop making sense. For now, the combination of architectural innovation, advanced packaging, and continued lithography improvements suggests several more nodes of headroom remain.