Silicon to System: How Semiconductor Chips Are Manufactured

01 From Sand to Silicon: The Wafer Foundation

Every microchip begins as quartz sand, which is reduced to metallurgical-grade silicon and then purified to semiconductor-grade polysilicon with a purity of 99.9999999 percent. This polysilicon is melted in a quartz crucible at approximately 1414 degrees Celsius, and a single-crystal silicon seed is dipped into the melt and slowly withdrawn while rotating. The silicon atoms attach to the seed in the same crystal orientation, growing a cylindrical single-crystal ingot or boule that can be up to 300mm in diameter and two meters long.

The boule is sliced into thin wafers using a diamond wire saw, then ground and polished to a mirror finish with surface flatness measured in nanometers. Each 300mm wafer yields hundreds or thousands of individual chips depending on die size. The purity of the starting material, the precision of the crystal growth, and the flatness of the wafer surface are all prerequisites for the nanometer-scale lithography that follows. A single defect in the crystal lattice can render an entire chip non-functional, which is why semiconductor fabs operate in cleanrooms with fewer than one particle per cubic foot of air.

02 Photolithography: Drawing Circuits With Light

Photolithography is the core process that defines the patterns of electronic circuits on the wafer. A photoresist material is spin-coated onto the wafer surface, and a mask containing the circuit pattern is aligned over the wafer. Light is projected through the mask onto the resist, chemically altering the exposed areas so they can be selectively dissolved away. The pattern that remains in the resist is then transferred to the underlying material through etching.

The resolution of photolithography is limited by the wavelength of the light used and the numerical aperture of the projection optics. For decades, the industry used ultraviolet light at 193nm wavelength produced by excimer lasers. The transition to extreme ultraviolet (EUV) lithography at 13.5nm wavelength, pioneered by the Dutch company ASML, enabled the production of chips at 7nm, 5nm, and now 3nm process nodes. EUV light is generated by blasting microscopic droplets of molten tin with a high-power laser 50,000 times per second, producing plasma that emits at the desired wavelength. The light is collected by the most precise mirrors ever manufactured and projected onto the wafer with positioning accuracy measured in picometers.

03 Deposition, Etching, and Ion Implantation

Between lithography steps, the wafer undergoes a series of material modification processes. Thin-film deposition grows layers of material onto the wafer through chemical vapor deposition (CVD) or physical vapor deposition (PVD). These layers form the insulators, conductors, and semiconductors that make up the circuit. Thermal oxidation grows silicon dioxide by exposing the wafer to oxygen or steam at high temperatures, creating a high-quality insulating layer directly from the silicon substrate.

Etching removes material selectively to define circuit features. Wet etching uses chemical solutions, while dry etching uses plasma or reactive ion etching for more precise control. The most advanced etching processes can remove material with atomic-layer precision, removing a single layer of atoms at a time. Ion implantation shoots dopant ions into the silicon to modify its electrical properties, creating the n-type and p-type regions that form transistors. The depth and concentration of the implanted ions are controlled by the ion energy and dose, with modern implants placing atoms within nanometers of the surface.

04 The Transistor: From Planar to FinFET to GAA

The fundamental building block of every chip is the transistor, and its physical structure has evolved dramatically as process nodes have shrunk. At nodes above 22nm, transistors were planar: the gate sat flat on top of the silicon channel. At 22nm, Intel introduced the FinFET, a three-dimensional transistor where the channel rises vertically as a fin, with the gate wrapping around three sides. This improved electrostatic control and reduced current leakage.

At the 3nm node and below, the industry is transitioning to gate-all-around (GAA) transistors, where the channel is a nanosheet surrounded on all four sides by the gate. GAA provides even better electrostatic control and allows continued scaling. Samsung began GAA production at 3nm in 2022, and TSMC is expected to use GAA at 2nm. The transition from one transistor architecture to another requires redesigning not just the transistor but the entire manufacturing process, including new deposition recipes, new etching chemistries, and new metrology techniques.

05 Packaging and the Chiplet Revolution

After the wafer is fully processed, it is tested, diced into individual die, and packaged. For decades, packaging meant placing a single die in a plastic or ceramic container and connecting it to external pins with wire bonds. Advanced packaging has transformed this step into a critical differentiator. Techniques such as flip-chip, through-silicon vias (TSVs), and hybrid bonding allow multiple die to be stacked vertically or placed side by side on a single substrate with micrometer-scale interconnects.

The chiplet approach divides a large monolithic die into smaller pieces manufactured on different process nodes and assembled in a single package. An AI accelerator might combine a 3nm compute die with 6nm I/O die and DRAM stacks, each optimized for its function. AMD's Epyc processors, Intel's Ponte Vecchio, and Nvidia's H100 all use chiplet designs. This approach improves yield (smaller die are less likely to have defects), reduces cost, and allows mixing technologies that cannot be fabricated on the same process. The packaging technology is now as important as the transistor technology in determining overall system performance.

06 The Economics of Fabs: Billions Per Factory

A leading-edge semiconductor fab costs between 15 and 20 billion dollars to build and takes two to three years to construct. The equipment inside, dominated by ASML lithography machines that cost 200 to 300 million dollars each, accounts for roughly 70 percent of the capital expenditure. A fab operates 24 hours a day, 365 days a year, and must produce millions of wafers to amortize its capital cost. The result is an industry with enormous barriers to entry: only three companies in the world (TSMC, Samsung, and Intel) can manufacture chips at the leading edge.

The concentration of manufacturing capacity in Taiwan, which produces over 90 percent of the world's most advanced chips, has become a geopolitical flashpoint. The US CHIPS Act, the European Chips Act, and Japan's semiconductor revitalization program are injecting hundreds of billions of dollars in subsidies to build domestic fabrication capacity. TSMC is building fabs in Arizona, Samsung in Texas, and Intel in Ohio, but these projects face challenges including workforce shortages, higher operating costs, and the question of whether customers will pay a premium for non-Taiwanese production.

07 The Future: Beyond 2nm and New Materials

As the industry approaches the 2nm node and beyond, the limits of silicon are becoming apparent. At these dimensions, quantum tunneling causes current leakage that increases power consumption and reduces reliability. Researchers are exploring new channel materials such as silicon-germanium, indium gallium arsenide, and two-dimensional materials like molybdenum disulfide that offer better electrical properties at small dimensions. Backside power delivery, which routes power connections through the bottom of the wafer rather than the top, frees up surface area for signal routing and is being introduced at the 2nm node by Intel (PowerVia) and TSMC.

The longer-term future may involve entirely new computing paradigms built on the same semiconductor manufacturing infrastructure. Photonic chips that use light instead of electrons for interconnects are being manufactured in limited quantities. Neuromorphic chips that mimic the brain's architecture are being explored by Intel and others. And the integration of AI into the manufacturing process itself, using machine learning for defect detection, process control, and yield optimization, is already changing how fabs operate. The chip that powers the next AI model may itself be designed and manufactured with the help of AI.