RISC-V at a Crossroads: The Open-Source Chip Architecture Fighting for Its Next Decade

01 A Berkeley Idea With a Blank-Page License

RISC-V began in 2010 as a research project at UC Berkeley, where Krste Asanovic and David Patterson's team needed a clean instruction set for teaching and research, unencumbered by the licensing terms of commercial architectures. What they produced was a deliberately minimal reduced instruction set computer (RISC) design: a small base integer instruction set, published under permissive open licenses, that anyone could implement in silicon without paying royalties.

The contrast with the incumbent model is stark. ARM Holdings and Intel license their instruction sets and, in many cases, validated core designs for fees and contractual terms that shape who is allowed to compete. RISC-V inverted that. The specification is free, the working groups that extend it operate in the open, and the only thing a company cannot do is call a non-conforming chip RISC-V without the compliance tests. It is standardization in the mold of the internet protocols, applied to processor design.

02 Modularity as Design Philosophy

The architecture's second defining decision was to make the base small and everything else optional. A RISC-V core implements a compact integer instruction set, then adds extensions as needed: multiplication and division, atomic operations, compressed 16-bit encodings for code density, single-precision or double-precision floating point, and vector operations for data-parallel workloads. A three-cent microcontroller can implement the base set and nothing else; a datacenter application processor can implement a dozen extensions on the same architectural spine.

This modularity is both the architecture's greatest strength and the root of its software problem. Because there is no single mandatory feature set beyond the base integer instructions, two RISC-V chips from different vendors can differ in exactly which extensions they support. The industry recognized the hazard early: the RVA22 profile, ratified in 2022, specifies a common set of extensions that application-class implementations are expected to carry, precisely so that a Linux distribution can target one profile instead of a combinatorial explosion of variants. Profiles are the architecture's mechanism for having chosen modularity and compatibility too, though adoption of a profile is not the same thing as its universal enforcement.

03 Where RISC-V Has Already Won

In markets where software expectations are thin, RISC-V has not merely entered but become the path of least resistance. Embedded controllers and microcontrollers were first: an open, royalty-free ISA is irresistible in devices with bill-of-materials margins measured in cents, and the base instruction set alone is sufficient for the job. Hard-disk and SSD storage controllers followed the same logic, and several major silicon vendors quietly switched their controller families to RISC-V cores without consumers ever noticing, which is the point.

Automotive is a growing beachhead, where RISC-V cores appear in everything from sensor interfaces to safety islands, drawn by the auditability of an open specification and freedom from supplier lock-in across decades-long platform lifetimes. And in China, RISC-V has reached consumer-facing silicon: laptops built on RISC-V application processors have shipped, and RISC-V cores have appeared inside smartphone companion and SoC silicon. By core count, the installed base is now in the billions, mostly invisible, doing unglamorous work.

04 Where It Still Struggles

The gaps are concentrated where the incumbents' moats are deepest. The first is application-class software. Three decades of commercial software, device drivers, and developer tooling assume ARM or x86. Windows-class desktop software in particular has no meaningful RISC-V story: the porting burden is large, the commercial incentive is thin until hardware volumes justify it, and volumes stay thin until software arrives. The chicken-and-egg problem that ARM solved for laptops across years of Apple-class investment is RISC-V's problem now, without an Apple.

The second gap is high-performance core design. An open instruction set removes licensing costs, but it does not remove the engineering cost of building a core that competes with the best superscalar out-of-order designs. The handful of companies that can build such cores have little incentive to give their designs away, so the open hardware commons remains rich in small cores and thin in flagship ones.

The third is the fragmentation problem that modularity created. Extensions multiply, profiles help but bind only by convention, and a software vendor targeting the ecosystem must reason about which feature sets actually exist in shipped silicon. The embedded world tolerates this easily; the application world, where a single binary must run everywhere, finds it corrosive.

05 The Geopolitics of an Open ISA

RISC-V's technical virtues made it a strategic object almost by accident. An architecture that cannot be embargoined, because the specification is public and freely implementable, is attractive to any country that fears being cut off from Western chip intellectual property. China's adoption push, formalized in state-backed programs from 2023 onward, treats RISC-V as a hedge against export controls on advanced silicon: an open ISA offers domestic chip designers a base on which to build, regardless of who controls ARM's licensing or x86's patents.

That has produced a reaction. Policymakers in the United States have debated whether RISC-V's openness constitutes a leak of strategic technology, an odd framing for a specification that is intentionally public, and Western governments have grown warier of the foundation that stewards it. The architecture is caught between two logics: the internet-protocol logic, in which openness made the standard universal and neutral, and the export-control logic, in which any technology a rival can use becomes a controlled good. How that tension resolves will shape RISC-V's governance as much as any technical roadmap.

06 What the Next Decade Requires

The optimistic scenario is straightforward to state and hard to execute. RISC-V needs profile discipline to hold, so that application software can target a small number of well-defined feature sets rather than a lattice of vendor variants. It needs at least one high-performance open core to anchor a serious application ecosystem. It needs a first commercial breakthrough on the desktop or laptop that makes porting mainstream software financially rational. And it needs its governance to survive great-power scrutiny without forking into rival national architectures, which would recreate the very fragmentation it was designed to escape.

The pessimistic scenario is also clear: RISC-V remains the world's most successful embedded ISA, ubiquitous in devices nobody names and invisible in markets where ARM and x86's ecosystems are self-reinforcing. Even that outcome would be an extraordinary achievement for a university project, but it would leave the deeper question unanswered: whether open, collaborative standardization can carry an ecosystem all the way to the top of computing, or whether the moats around software ecosystems are simply too deep to cross with openness alone.